SAMSUNG's ASIC design methodology and services help you achieve first-time silicon success with multi-million-gate ASIC using very deep sub-micron (VDSM) technology. In addition to creating high-density, high-performance ASIC chips, you'll have assistance integrating the world’s most advanced memory into your ASICs. For System-on-Chip (SoC) designs, static verification methodology will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressures.

To deal with VDSM issues, we support state-of-the-art, back-end CAD tools, both commercial and in-house. Our Design-for-Testability (DFT) methodology takes you through all phases of test insertion, test pattern generation and fault grading to get ultra-high test coverage. For a VDSM technology, interconnect delays can become dominant. Resistance shielding and the resulting effective capacitance effect for cell delay are important. SAMSUNG's ASIC solution provides a best-of-both-worlds approach that combines CubicDelay (SEC's common delay calculator) and Star-RCXT. Our design methodology includes IR-drop analysis and SI analysis and optimization.

SAMSUNG offers a Synopsys-synthesis-friendly library. It contains primitive cells that implement design-compiler frequently used combinational functions. By using synthesis-friendly cells, the design compiler can give you a smaller, higher-performance design.